1. Field of the Invention
The present invention generally relates to the art of microelectronic integrated circuits, and more specifically to a microelectronic integrated circuit structure and method using three directional interconnect routing based on a hexagonal geometry.
2. Description of the Related Art
Microelectronic integrated circuits consist of a large number of electronic components that are fabricated by layering several different materials on a silicon base or wafer. The design of an integrated circuit transforms a circuit description into a geometric description which is known as a layout. A layout consists of a set of planar geometric shapes in several layers.
The layout is then checked to ensure that it meets all of the design requirements. The result is a set of design files in a particular unambiguous representation known as an intermediate form that describes the layout. The design files are then converted into pattern generator files that are used to produce patterns called masks by an optical or electron beam pattern generator.
During fabrication, these masks are used to pattern a silicon wafer using a sequence of photolithographic steps. The component formation requires very exacting details about geometric patterns and separation between them. The process of converting the specifications of an electrical circuit into a layout is called the physical design. It is an extremely tedious and an error-prone process because of the tight tolerance requirements and the minuteness of the individual components.
Currently, the minimum geometric feature size of a component is on the order of 0.5 microns. However, it is expected that the feature size can be reduced to 0.1 micron within several years. This small feature size allows fabrication of as many as 4.5 million transistors or 1 million gates of logic on a 25 millimeter by 25 millimeter chip. This trend is expected to continue, with even smaller feature geometries and more circuit elements on an integrated circuit, and of course, larger die (or chip) sizes will allow far greater numbers of circuit elements.
Each microelectronic circuit cell includes a plurality of pins or terminals, each of which is connected to pins of other cells by a respective electrical interconnect wire network or net. A goal of the optimization process is to determine a cell placement such that all of the required interconnects can be made, and the total wirelength and interconnect congestion are minimized.
As illustrated in FIG. 1, a conventional microelectronic integrated circuit 10 comprises a substrate 12 on which a large number of microelectronic circuits are formed. These circuits include large functional macroblocks such as indicated at 14 which may be central processing units, input-output devices or the like. A typical integrated circuit further comprises a large number of cells 16 that are arranged in a generally rectangular pattern in the areas of the substrate 12 that are not occupied by macroblocks.
The cells 16 may comprise individual logic gates, or more preferably may each comprise a plurality of logic gates that are interconnected to form functional blocks. Typically, a cell library consisting of standardized cells that perform desired logical operations are provided and are combined with other cells to form an integrated circuit having the desired functionality.
The cells 16 have terminals 18 to provide interconnections to other cells 16 on the substrate 12. Interconnections are made via vertical electrical conductors 20 and horizontal electrical conductors 22 that extend between the terminals 18 of the cells in such a manner as to achieve the interconnections required by the netlist of the integrated circuit 10. It will be noted that only a few of the elements 16, 18, 20 and 22 are designated by reference numerals for clarity of illustration.
In conventional integrated circuit design, the electrical conductors 20 and 22 are formed in vertical and horizontal routing channels (not designated) in a rectilinear (Manhattan) pattern. Thus, only two directions for interconnect routing are provided, although several layers of conductors extending in the two orthogonal directions may be provided to increase the space available for routing.
As discussed above, a goal of routing is to minimize the total wirelength of the interconnects, and also to minimize routing congestion. Achievement of this goal is restricted using conventional rectilinear routing because diagonal connections are not possible. A diagonal path between two terminals is shorter than two rectilinear orthogonal paths that would be required to accomplish the same connection.
Another drawback of conventional rectilinear interconnect routing is its sensitivity to parasitic capacitance. Since many conductors run in the same direction in parallel with each other, adjacent conductors form parasitic capacitances that can create signal crosstalk and other undesirable effects.